1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of metallization layers, wherein a metal is deposited over a patterned dielectric layer and excess metal is subsequently removed by chemical mechanical polishing (CMP).
2. Description of the Related Art
In every new generation of integrated circuits, device features are further reduced, whereas the complexity of the circuits steadily increases. Reduced feature sizes not only require sophisticated photolithography methods and advanced etch techniques to appropriately pattern the circuit elements, but also places an ever-increasing demand on deposition techniques. Presently, the minimum feature sizes approach 0.1 μm or even less, which allows the fabrication of fast-switching transistor elements covering only a minimum of chip area. However, as a consequence of the reduced feature sizes, the available floor space for the required metal interconnects decreases while the number of necessary interconnections between the individual circuit elements increases. As a result, the cross-sectional area of metal connects decreases and this makes it necessary to replace the commonly used aluminum by a metal that allows a higher current density at a reduced electrical resistivity to obtain reliable chip interconnects with high quality. In this respect, copper has proven to be a promising candidate due to its advantages, such as low resistivity, high reliability, high heat conductivity, relatively low cost and a crystalline structure that may be controlled to obtain relatively large grain sizes. Furthermore, copper shows a significantly higher resistance against electromigration and, therefore, allows higher current densities while the resistivity is low, thus allowing the introduction of lower supply voltages.
Despite the many advantages of copper compared to aluminum, semiconductor manufacturers in the past have been reluctant to introduce copper into the manufacturing sequence for several reasons. One major issue in processing copper in a semiconductor line is the copper's capability of readily diffusing in silicon and silicon dioxide at moderate temperatures. Copper diffused into silicon may lead to a significant increase in the leakage current of transistor elements, since copper acts as a deep-level trap in the silicon band-gap. Moreover, copper diffused into silicon dioxide may compromise the insulating properties of silicon dioxide and may lead to higher leakage currents between adjacent metal lines, or may even form shorts between neighboring metal lines. Thus, great care must be taken to avoid any contamination of silicon wafers with copper during the entire process sequence.
A further issue arises from the fact that copper may not be effectively applied in greater amounts by deposition methods, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), which are well-known and well-established techniques in depositing other materials, such as aluminum. Accordingly, copper is now commonly applied by a wet process, such as electroplating, which provides, compared to electroless plating, the advantages of a higher deposition rate and a less complex electrolyte bath. Although at a first glance electroplating seems to be a relatively simple and well-established deposition method due to the great amount of experience gathered in the printed wiring board industry during decades, the demand of reliably filling high aspect ratio openings with dimensions of 0.1 μm and less, as well as wide trenches having a lateral extension in the order of micrometers, renders electroplating of copper, as well as other metals that may be used in metallization layers, a highly complex deposition method, in particular as subsequent process steps, such as chemical mechanical polishing and any metrology processes, directly depend on the quality of the electroplating process.
With reference to FIGS. 1a–1b, a typical process sequence for manufacturing a metallization layer will now be described. According to FIG. 1a, a semiconductor device 100 comprises a substrate 101 including circuit elements, such as transistors, resistors, capacitors and the like, which, for the sake of simplicity, are not depicted in FIG. 1a. A dielectric layer 102 is formed above the substrate 101 and is separated therefrom by an etch stop layer 103. For example, the dielectric layer 102 may be comprised of silicon dioxide, whereas the etch stop layer 103 may be comprised of silicon nitride. In other cases, the dielectric layer 102 and possibly the etch stop layer 103 may be comprised of a so-called low-k dielectric having a permittivity that is significantly lower than that of silicon dioxide and silicon nitride. In the dielectric layer 102, openings 105 are formed as vias and trenches. The dimensions of the openings 105 as well as the spacing and their position on a die area of the substrate 101 are determined by the circuit design of a corresponding integrated circuit. The dielectric layer 102 may further include an opening 104 provided as a relatively wide trench. Moreover, the dielectric layer 102 may contain a substantially non-patterned region 106. As with the openings 105, the dimension and the position of the trench 104 and of the non-patterned region 106 is substantially determined by the circuit design.
The methods for forming the semiconductor device 100 as depicted in FIG. 1a are well established in the art and may include well-known deposition, lithography and etch techniques. In particular, the opening 105 may be formed in a first selective etch step within the dielectric layer 102, wherein the etch process stops on or in the etch stop layer 103. The opening 105 may then be formed in the etch stop layer 103 by a separate etch process designed to selectively remove the material of the layer 103. Thereafter, in a further etch step, the upper portion of the opening 105 and the opening 104 may be formed in a common etch step.
FIG. 1b schematically shows the semiconductor device 100 in an advanced manufacturing stage with a metal layer, such as copper layer 107, formed over the dielectric layer 102, wherein a barrier layer and a seed layer, which for convenience are commonly denoted by 108, is disposed between the metal layer 107 and the dielectric layer 102. The barrier/seed layer 108 may be comprised of two or more sub-layers containing materials such as tantalum, tantalum nitride, titanium, titanium nitride, combinations thereof, and the like. The seed layer may be comprised of, for example, copper.
The barrier/seed layer 108 may be formed by chemical vapor deposition, atomic layer deposition or physical vapor deposition followed by, for example, a sputter deposition process to form the seed layer as the final sub-layer of the barrier/seed layer 108. Thereafter, the metal layer 107 is deposited, wherein, as previously noted in context with copper, a wet-chemical process may preferably be employed so as to effectively provide large amounts of metal at reasonable deposition rates. For copper, electroplating is typically the presently preferred deposition method due to an increased deposition rate and a moderately complex electrolyte bath compared to electroless plating.
For reliable metal interconnects, it is not only important to deposit the copper as uniformly as possible over the entire surface of a 200, or even 300, mm diameter substrate, but it is also important to reliably fill the openings 105 and 104 that may have an aspect ratio of approximately 10:1, without any voids or defects. As a consequence, it is essential to deposit the copper in a highly non-confornmal manner. Accordingly, great efforts have been made to establish an electroplating technique that allows a highly non-conformal deposition of a metal, such as copper, in which openings, especially the small-sized vias and trenches 105, are filled substantially from bottom to top. It has been recognized that such a fill-in behavior may be obtained by controlling the deposition kinetics within the openings 105, 104 and on the horizontal portions, such as the non-patterned region 106. This is commonly achieved by introducing additives into the electrolyte bath to influence the rate of copper ions that deposit on the respective locations. For example, an organic agent of relatively large, slow-diffusing molecules, such as polyethylene glycol, may be added to the electrolyte and preferentially absorbs on flat surface and comer portions. Hence, contact of copper ions at these regions is reduced and thus the deposition rate is decreased. A correspondingly acting agent is also often referred to as a “suppressor.” On the other hand, a further additive, including smaller and faster-diffusing molecules, may be used that preferentially absorbs within the openings 105, 104 and enhances the deposition rate by offsetting the effects of the suppressor additive. A corresponding additive is often also referred to as an “accelerator.” In addition to using an accelerator and a suppressor, so-called levelers or brighteners are used to strive to reach a high degree of uniformity and to enhance the surface quality of the metal layer 107. Moreover, a simple DC deposition, i.e., deposition by supplying a substantially constant current, may not suffice to achieve the required deposition behavior despite the employment of accelerator, suppressor and/or leveler additives. Instead, the so-called pulse reverse deposition has become a preferred operation mode in depositing copper. In the pulse reverse deposition technique, current pulses of alternating polarity are applied to the electrolyte bath so as to deposit copper on the substrate during forward current pulses and to release a certain amount of copper during reversed current pulses, thereby improving the fill capability of the electroplating process. By these complex plating processes, the openings 105, 104 may be reliably filled with copper. It turns out, however, that the finally-obtained topography of the metal layer 107 depends on the underlying structure. Despite the employment of the pulse reverse method and a sophisticated chemistry including varying amounts of suppressors, accelerators and levelers, an enhanced deposition of metal is obtained over patterned regions, such as the openings 104, 105, as opposed to the non-patterned region 106. It is believed that a non-uniform distribution of the additives, especially of the accelerators in the vicinity of the openings 104, 105, leads to a further continuation of the deposition kinetics occurring within the openings 104, 105 even if these openings are already completely filled, thereby causing an enhanced deposition rate at these areas until finally the additives are uniformly distributed.
The structure-dependent topography of the metal layer 107 may then lead to process non-uniformity during a subsequent chemical mechanical polishing (CMP) process, since exposed areas of the metal layer 107 may experience an increased downforce, as indicated by arrows 109, during the polishing process. The removal process, therefore, preferably starts over the openings 104, 105 and may continue at a higher removal rate compared to the non-patterned region 106. Consequently, clearing of the surface of the region 106 is delayed and a substantial “overpolish” time is required to substantially completely remove any metal residues from the region 106. This may cause an increased material removal in the openings 104, 105, which is also referred to as “dishing,” and may also lead to increased removal of dielectric material of the layer 102 in the vicinity of the openings 104, 105, also known as erosion. In addition to these deleterious effects, the non-uniformity of the metal removal may also affect any endpoint detection methods, such as methods based on optical signals obtained by light reflected from the metal layer 107 during the polish process, based on the motor current required to establish a relative motion between the substrate 101 and a polishing pad, or based on other friction related or otherwise generated endpoint signals. That is, the corresponding endpoint signals may exhibit a less steep slope and may therefore exacerbate the assessment of the end of the polishing process. Since CMP is in itself a highly complex process, the final result of the polishing process and hence the quality of the metal lines formed in the openings 104, 105 not only depends on the CMP parameters but is also strongly influenced by the properties of the metal layer 107. For these reasons, it is frequently proposed to provide a “dummy” pattern in the non-patterned region 106 so as to achieve similar deposition conditions as over the openings 104, 105. Although this approach may significantly relax the above-identified non-uniformity issues, the additionally generated metal regions may add parasitic capacitance to the circuit, thereby reducing the operating speed thereof, and may in many cases render this solution less than desirable.
In view of the above-mentioned problems, a need exists to provide an electroplating process that minimizes the burden on the subsequent CMP process.